In the field of electronics various electronic design automation (EDA) tools are useful for automating the process by which integrated circuits, multi-chip modules, boards, etc., are designed and manufactured. In particular, electronic design automation tools are useful in the design of standard integrated circuits, custom integrated circuits (e.g., ASICs, ASSPs), and in the design of custom configurations for programmable integrated circuits. Integrated circuits that may be programmable by a customer to produce a custom design for that customer include programmable logic devices (PLDs). Programmable logic devices refer to any integrated circuit that may be programmed to perform a desired function and include programmable logic arrays (PLAs), programmable array logic (PAL), field programmable gate arrays (FPGA), complex programmable logic devices (CPLDs), and a wide variety of other logic and memory devices that may be programmed. Often, such PLDs are designed and programmed by a design engineer using an electronic design automation tool that takes the form of a software package.
Once a design is generated for a PLD and the PLD is programmed a printed circuit board (PCB) designer places and routes the PLD on the printed circuit board or in the system for which it is intended. During the course of placing and routing an FPGA (or any PLD) on a printed circuit board the board designer attempts to simplify the routing on the board as much as possible in order to use fewer layers. For example, a complex routing on a board might require six or more layers, while a less complex routing might only need three. Fewer layers in a printed circuit board is desirable as it lessens the complexity, reduces problems associated with multiple layers and reduces the cost of the printed circuit board.
FPGAs (as well as many PLDs) provide a flexible capability of configuring the input/output elements (I/O elements) of the device based upon the capabilities of the chip and the designer's needs. Thus, in order to simplify the routing of a printed circuit board, and to reduce the number of layers needed, a board designer takes advantage of the configurability of the I/O elements of an FPGA in the course of placing and routing such a device on a board. In other words, to minimize the board routing layers, the board designer might need to change the pin locations of an FPGA design. But, due to the complexity of FPGAs, the board designer must adhere to certain operating rules and conditions specified by the FPGA vendor that are not always intuitive.
Currently, the design of a printed circuit board layout involving an FPGA is very much a trial and error process. Pin swap information (which tells the board designer which pins can be swapped successfully) is manually accumulated by the designer by referencing data sheets and application notes that describe the operating specifications for the I/O elements. These are often paper documents that require manual review by the designer before a pin swap can be confidently performed. An illegal pin swap ends up wasting time because a compilation must be performed, an error message generated, and then the design must be redone correctly. The problem is compounded for highly complex FPGAs in that there will likely be different designers for the FPGA and for the printed circuit board.
Further, should a board designer require a change in the I/O element configuration of an FPGA implementation the FPGA designer must then redesign the FPGA and resubmit his or her design to the board designer. The board designer then attempts to work with the new design and may require even more iterations of this back-and-forth process. It can take hours or days of the engineers' time to work out a suitable FPGA design for a particular printed circuit board.
Accordingly, there is a need to be able to provide a printed circuit board designer with accurate pin swap information for an FPGA in an automated fashion such that he or she can more easily integrate the FPGA onto a printed circuit board.